The present invention relates generally to APSK (amplitude and phase shift keyed) modulation receivers, and more specifically to a clock recovery circuit for APSK signals.
As described in H. Tomita et al "Preambleless Demodulator For Satellite Communications," open-loop phase estimation is known for detecting a phase difference between transmitted clock and local clock. Such open-loop phase estimation is implemented with envelope detection, phase correlation, low-pass filtering and arctangent calculation. While satisfactory for detecting a phase difference during the period of a short packet, the phase estimation technique is not capable of tracking slow phase variations which may occur during a continuous transmission. Another technique which has been extensively used for recovering clock timing is the phase locked loop implemented by a phase detector, a loop filter, and a voltage controlled oscillator. An analog-to-digital converter is clocked by the VCO for sampling a received APSK signal and supplying the samples to the phase detector in which the phase difference between the sampling clock and the transmitted clock is detected. However, the PLL approach takes long to establish clock synchronization.